High-sensitivity low-energy thermal aware system for next generation integrated systems


Two primary methods are used to achieve next generation integrated systems, a large number of deeply scaled devices and die stacking. High power densities and thermal issues such as long heat conduction paths are produced, which, in turn, can dramatically degrade performance, reliability, leakage current, and system robustness. To manage the system workload and protect the system from overheating, methods such as allocating heat conduction paths and specialized cooling systems are used. These systems need to be supported with a temperature aware capability to allocate and properly respond to critical hot spots.


A thermal aware system can be achieved by distributing a large number of on-chip thermal sensors. These on-chip thermal sensors should be small in size, low power, high speed, sensitive, and accurate over a wide temperature range. The on-chip thermal sensors should be appropriately placed to accurately capture local hot spots. The location of the thermal sensors depends upon the sensor characteristics, system requirements, IC package, and cooling techniques. A small number of thermal sensor nodes are typically located around an IC, particularly near potential hot spots to support a thermal aware system. For instance, Intel utilizes one thermal sensor per core in the Xeon 5400 series, while 25 thermal sensors are embedded within the IBM POWER6 processor. The use of a few thermal sensors, however, limits the ability to fully monitor the significant spatial and dynamic temperature variations across an integrated system. Thermal aware systems manage the located distributed thermal sensor nodes around an IC, dynamically controlling the system workload. These systems, however, utilize a software based management system which do not respond to individual thermal sensor nodes. In addition, the response time of these software solutions is long and consumes significant power; hence hardware solutions are desirable.



We have developed an integrated system to support a thermal aware capability, where multiple thermal sensor nodes are distributed across an IC in a grid structure. The sensor nodes are based on hybrid spintronic/CMOS technology, and exhibit a thermal linearity of 0.9 and thermal sensitivity of 4.8 mv/K over a temperature range of -55 oC to 125 C. We have designed a system of 1,045 thermal sensors distributed in a 32 x 32 grid structure that consumes approximately 500 pJ, providing a low energy and high sensitivity thermal aware system for next generation integrated systems.


A. G. Qoutb and E. G. Friedman, "Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems," IEEE Transactions on Very Large Scale Integration Systems, Volume 28, No. 6, pp. 1505 - 1512, June 2020.

URV Reference Number: 2-20022
Patent Information:
Computer Hardware
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
Eby Friedman
Abdelrahman Qoutb