Power Network On-Chip for Scalable Power Delivery

Technology Summary

 

Power network on-chip is a systematic methodology for on-chip power delivery and management that provides enhanced power control and real-time management of resource sharing, while addressing primary power delivery concerns, such as scalability and energy efficiency of power deliver system, quality of power, and limited on-chip area.

URV Reference Number: 2-11144-14030
Patent Information:
Category(s):
Computer Hardware
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
585.273.3250
curtis.broadbent@rochester.edu
Inventors:
Eby Friedman
Inna Vaisband
Keywords: