Flexible, Decoupled Hardware-Accelerated Transactional Memory

This is a new architecture for multi-processor computers using transactional memory.



Today’s multi-core computers require explicit parallel programming, which is difficult. This transactional memory (TM) system can be used in computers with multi-core processors to reduce programming complexity and increase parallel program scalability.



Current software TM systems run on stock processors and provide substantial flexibility, but incur significant overhead for data versioning and validation in the face of conflicting transactions. Hardware TM designs have been proposed with the advantage of speed, but embed significant amounts of policy in silicon, and lose flexibility.


This invention, FlexTM (Flexible Transaction Memory) coordinates four decoupled hardware mechanisms: read and write signatures, per-thread conflicts summary tables, programmable data isolation, and alert-on-update. All mechanisms are software accessible to enable virtualization and to support transactions of arbitrary length. In simulation testing, FlexTM has exhibited a five-fold speedup over high quality software TM, with no loss in policy flexibility.

URV Reference Number: 1-11114-08007
Patent Information:
Title Country Patent No. Issued Date
Mechanisms to Support Flexible Decoupled Transactional Memory United States 8,661,204 2/25/2014
Computer Software
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
Sandhya Dwarkadas
Arrvindh Shriraman
Michael Scott