This is an improved CMOS image sensor, which is 40 times faster than conventional CMOS image sensors, operating from a 3.3 V power supply, with significantly lower 1/f noise. The circuit utilizes the standard APS design and retains the high fill factor in a 0.35 µm standard CMOS process. In this current sensing active pixel (CSAP) sensor, the negative feedback circuit that connects the readout of the pixel increases the current driving capabilities and readout speed.
For image sensors in digital cameras and in cell phone cameras.
The first advantage of the in-pixel transistor current sampling is the high speed of video frame capture and faster electronic shutter, which is important in special applications. The more important advantage of the for all image applications is that, due to its high speed, the proposed design significantly reduces the 1/f noise of the source follower transistor because it can more effectively employ correlated double sampling (CDS) to reduce 1/f noise, because of the significantly decreased the time interval between successive measurements in the correlated double sampling. The design also reduces fixed pattern noise caused by gain variation by increasing the effective open-loop gain of the source-follower amplifier. An additional practical advantage is that this design improvement retains the basic chip architecture of the CMOS APS (Active Pixel Sensor) devices which are the mainline commercial chips used in digital cameras and cell phones today, and will be straightforward to implement.