Method and Apparatus to Reduce Noise Fluctuations in On-Chip Power Distribution Networks

The is a circuit design technique for reducing the noise fluctuations in on-chip power distribution networks when digital circuits are switched, producing current peaks and voltage fluctuations in power supply lines due to the inductive behavior of interconnects.

For use in many CMOS circuties for reducing on-chip or chip-to-package noise  which results when digital circuits are switched.
Previous attempts to reduce this noise which is becoming increasing a limiting factor in high speed, very deep submicrometer circuit designs, have focused on ground bounce, by lowering the inductance in the power and ground paths by utilizing the substrate conduction or controlling the slew rate. Others have included a routing method to distribute the ground bounce among the pods or using decoupling capacitors to maintain voltage on the P/G rails. In this invention, an on-chip noise-free ground is added to divert ground noise from the sensitive nodes and an on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, is placed on the die to provide an additional ground path. Ground bounce reductions of almost 52% and 68% are shown for a single frequency noise source. The technique shows a strong tolerance to capacitance variations and is effective for both single frequency and random voltage fluctuation on the ground terminal.

URV Reference Number: 2-11144-05031
Patent Information:
Computer Hardware
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
Eby Friedman
Mikhail Popovich
Radu Secareanu
Olin Hartin