Adaptive Issue Queue for Reduced Power at High Performance

Brief Description:
This is a method to reduce power consumption in microprocessor functional modules which have dedicated memory, buffer, or queue resources by forming a queue to those resources, based on dynamic statistics of the memory module activity, and depending on need or activity, the modules are adaptively changed in size.

This concept is for super-scalar micro-processors.  Such processors can accept instructions similar to a scalar processor, but has the additional capability to fetch, issue and execute multiple instructions in a given machine cycle.  The issue queue provides ready instruction to the execution units.

Issue queues typically burn a lot of power because the queue is implemented with a continuously clocked array of flip-flops and latches, and the conventional implemenation wastes additional power by not exploiting the exploiting the dynamically changing requirements of the executing work load.  The proposed adaptive issue queue achieves significant power reduction without appreciable performance loss or significant additional hardware.
URV Reference Number: 1-11114-1067
Patent Information:
Title Country Patent No. Issued Date
Adaptive Issue Queue for Reduced Power at High Performance United States 7,865,747 1/4/2011
Computer Hardware
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
David Albonesi
Alper Buyuktosunoglu
Pradip Bose
David Brooks
Peter Cook
Stanley Schuster