Electrical Reconfigurability and an Electrical Reconfigurable Logic Gate Intrinsically Enabled by Spin-Orbit Materials
Web Published:
11/14/2019
An integrated logic device includes a channel having an interconnect section and a pair of spin-orbit segments connected to the interconnect section at either end of the interconnect section. A P structure includes a P magnet disposed on a surface of a spin-orbit segment. A tunneling barrier is disposed between the P magnet and a Rp magnetic reference layer. A Q structure includes a Q magnet disposed on a surface of the other spin-orbit segment. A tunneling barrier is disposed between the Q magnet and a Rq magnetic reference layer. A method of integrated logic spin-orbit perpendicular-anisotropy (SOPE) gate device operation is also described.
URV Reference Number: 2-18071
Patent Information:
Title |
Country |
Patent No. |
Issued Date |
Method of Electrical Reconfigurability and an Electrical Reconfigurable Logic Gate Device Intrinsically Enabled by Spin-Orbit Materials |
United States |
10,447,277 |
10/15/2019 |
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