Programmable Memory Controller
Web Published:
11/14/2019
One embodiment includes a programmable memory controller. The programmable memory controller includes a request processor that comprises a first domain-specific instruction set architecture (ISA) for accelerating common requests. A transaction processor comprises a second domain-specific ISA for accelerating transaction processing tasks. A dedicated command logic module inspects each memory command to a memory device and stalls particular commands for meeting timing constraints for application specific control of the memory device.
URV Reference Number: 1-11114-14004
Patent Information:
Title |
Country |
Patent No. |
Issued Date |
Programmable Memory Controller |
United States |
9,256,369 |
2/9/2016 |
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Inventors:
Keywords:
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