Magnetoresistive Dynamic Random Access Memory Cell



A magnetoresistive dynamic random access memory (MDRAM) cell is described. A hybrid memory cell includes a first transistor having a first source/drain electrode coupled to a charge storage node and a gate of a second transistor. A first transistor second source/drain electrode is coupled to a dynamic bit-line, and a gate of the first transistor coupled to a dynamic bit word-line. A resistive memory element is coupled between a select line and the second transistor first source/drain electrode. A third transistor includes a third transistor first source/drain electrode which is coupled to a second source/drain electrode of the second transistor. A third transistor second source/drain electrode is coupled to a nonvolatile bit-line. A gate of the third transistor is coupled to a nonvolatile bit word-line. A memory array of hybrid memory cells and a hybrid memory cell method is also described.


See M. Kazemi and M. F. Bocko, "gMRAM: Gain-cell magnetoresistive random access memory for high density embedded storage and in-situ computing," 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, 2017, pp. 405-408.



URV Reference Number: 2-17070
Patent Information:
Computer Hardware
For Information, Contact:
Curtis Broadbent
Licensing Manager
University of Rochester
Mohammad Kazemi