This is a hybrid approach, in which hardware is used to accelerate a transactional memory implementation of a multi-core computer, controlled fundamentally by software.
The computer industry is turning to multi-core and multi-threaded processors to increase performance. These multi-core processors require explicit parallel programming, which is difficult. Transactional memory (TM) systems are needed for multi-core processors to increase parallel program scalability and reduce programming complexity.
Current software TM systems run on stock processors and provide substantial flexibility, but incur significant overhead for data versioning and validation in the face of conflicting transactions. Hardware TM designs have been proposed with the advantage of speed, but embed significant amounts of policy in silicon, and lose flexibility.
The invention encompasses two hardware innovations and two levels of compliance. A lite form exploits only one of the hardware innovations: alert-on-invalidate-cache lines. A full form exploits both alert-on-invalidate and the second innovation: threatened-and-protected-cache lines. Lite is expected to be significantly faster than a software TM and significantly simpler than hardware TM. Specifically, it avoids most of the cost of validation while remaining 100% compatible with existing bus and coherence protocols. Our full TM is comparable in complexity to hardware TM but, like Lite, significantly more flexible. Both variants leave software in charge of almost all matters of policy, including conflict detection, contention management, deadlock and livelock avoidance, nesting, virtualization, and choice of data granularity. With respect to conflict detection in particular, our TM permits optimistic read-write and write-write sharing without requiring any global consensus algorithm in the cache coherence protocol.