This analog to digital convertor (ADC) is designed to reduce the impact of substrate noise, when the noise-sensitive analog circuits and the noise-generating digital circuits are placed closely together on a common substrate.
This sigma-delta analog to digital converter (ADC) is to be used in integrated system-on-a-chip (SOC) circuits requiring high resolution and low to moderate bandwidth.
The first design studies and simulations of the new architecture show an overall improvement in signal to noise ratio of 14 dB. The proposed design is not a major digression from the mature conventional sigma-delta ADC technology. and it also eliminates other effects of integrator op-amp non-idealities, such as 1/f noise, DC offset and all even-order non-linearities.
This design will compete with the conventional sigma delta ADCs for high resolution applications because the noise suppression and signal-to-noise advantage increases the dynamic range. Moreover because the design can tolerate non-linear effects, the circuit does not need to be driven at high current and hence will perform at significantly lower power consumption.
This is an improvement to an earlier related technology 2-11144-1080.