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Method and Apparatus to Reduce Noise Fluctuations in On-Chip Power Distribution Networks
The is a circuit design technique for reducing the noise fluctuations in on-chip power distribution networks when digital circuits are switched, producing current peaks and voltage fluctuations in power supply lines due to the inductive behavior of interconnects.ApplicationsFor use in many CMOS circuties for reducing on-chip or chip-to-package noise...
Published: 6/9/2021   |   Inventor(s): Eby Friedman, Mikhail Popovich, Radu Secareanu, Olin Hartin
Keywords(s):  
Category(s): Computer Hardware